SUD50N04-8M8P features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet ? 100 % uis tested ? 100 % r g tested ? pwm optimized ? compliant to rohs directive 2002/95/ec applications ? lcd display backlight inverters ? dc/dc converters product summary v ds (v) r ds(on) ( ) i d (a) a q g (typ.) 40 0.0088 at v gs = 10 v 50 16 nc 0.0105 at v gs = 4.5 v 50 to-252 s gd top v ie w drain connected to ta b orderin g information: sud50 n 04- 8 m 8 p-4ge3 (lead (p b )-free and halogen-free) n-channel mosfet g d s notes: a. package limited. b. surface mounted on 1" x 1" fr4 board. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 40 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 50 a a t c = 70 c 44 t a = 25 c 14 b t a = 70 c 11.2 b pulsed drain current i dm 100 continuous source-drain diode current t c = 25 c i s 40 t a = 25 c 2.6 b single pulse avalanche current l = 0.1 mh i as 30 avalanche energy e as 45 mj maximum power dissipation t c = 25 c p d 48.1 w t c = 70 c 30.8 t a = 25 c 3.1 b t a = 70 c 2.0 b operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b steady state r thja 32 40 c/w maximum junction-to-case steady state r thjc 2.1 2.6 n-channel 40 v (d-s) mosfet www.freescale.net.cn 1 / 9 vishay siliconix SUD50N04-8M8P document number: 68647 s10-0109-rev. b, 18-jan-10 www.vishay.com 1 n-channel 40-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet ? 100 % uis tested ? 100 % r g tested ? pwm optimized ? compliant to rohs directive 2002/95/ec applications ? lcd display backlight inverters ? dc/dc converters product summary v ds (v) r ds(on) ( : ) i d (a) a q g (typ.) 40 0.0088 at v gs = 10 v 50 16 nc 0.0105 at v gs = 4.5 v 50 to-252 s gd top v ie w drain connected to ta b orderin g information: sud50 n 04- 8 m 8 p-4ge3 (lead (p b )-free and halogen-free) n-channel mosfet g d s notes: a. package limited. b. surface mounted on 1" x 1" fr4 board. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 40 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 50 a a t c = 70 c 44 t a = 25 c 14 b t a = 70 c 11.2 b pulsed drain current i dm 100 continuous source-drain diode current t c = 25 c i s 40 t a = 25 c 2.6 b single pulse avalanche current l = 0.1 mh i as 30 avalanche energy e as 45 mj maximum power dissipation t c = 25 c p d 48.1 w t c = 70 c 30.8 t a = 25 c 3.1 b t a = 70 c 2.0 b operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b steady state r thja 32 40 c/w maximum junction-to-case steady state r thjc 2.1 2.6
notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 40 v v ds temperature coefficient v ds /t j i d = 1.0 ma 44 mv/c v gs(th) temperature coefficient v gs(th) /t j - 5.9 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.5 3.0 v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 40 v, v gs = 0 v 1 a v ds = 40 v, v gs = 0 v, t j = 70 c 20 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 50 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 20 a 0.0069 0.0088 v gs = 4.5 v, i d = 15 a 0.0084 0.0105 forward transconductance a g fs v ds = 15 v, i d = 15 a 75 s dynamic b input capacitance c iss v ds = 20 v, v gs = 0 v, f = 1 mhz 2400 pf output capacitance c oss 260 reverse transfer capacitance c rss 100 total gate charge q g v ds = 20 v, v gs = 10 v, i d = 20 a 37 56 nc v ds = 20 v, v gs = 4.5 v, i d = 20 a 16 24 gate-source charge q gs 6.5 gate-drain charge q gd 4.5 gate resistance r g f = 1 mhz 2.5 5.5 8.5 tu r n - o n d e l ay t i m e t d(on) v dd = 20 v, r l = 1 i d ? 20 a, v gen = 4.5 v, r g = 1 30 45 ns rise time t r 15 25 turn-off delay time t d(off) 45 70 fall time t f 15 25 tu r n - o n d e l ay t i m e t d(on) v dd = 20 v, r l = 1 i d ? 20 a, v gen = 10 v, r g = 1 915 rise time t r 510 turn-off delay time t d(off) 40 60 fall time t f 510 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 40 a pulse diode forward current a i sm 100 body diode voltage v sd i s = 10 a 0.81 1.2 v body diode reverse recovery time t rr i f = 20 a, di/dt = 100 a/s, t j = 25 c 22 35 ns body diode reverse recovery charge q rr 14 25 nc reverse recovery fall time t a 11 ns reverse recovery rise time t b 11 SUD50N04-8M8P n-channel 40 v (d-s) mosfet www.freescale.net.cn 2 / 9 www.vishay.com 2 document number: 68647 s10-0109-rev. b, 18-jan-10 vishay siliconix SUD50N04-8M8P notes: a. pulse test; pulse width d 300 s, duty cycle d 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 40 v v ds temperature coefficient ' v ds /t j i d = 1.0 ma 44 mv/c v gs(th) temperature coefficient ' v gs(th) /t j - 5.9 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.5 3.0 v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 40 v, v gs = 0 v 1 a v ds = 40 v, v gs = 0 v, t j = 70 c 20 on-state drain current a i d(on) v ds t 5 v, v gs = 10 v 50 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 20 a 0.0069 0.0088 : v gs = 4.5 v, i d = 15 a 0.0084 0.0105 forward transconductance a g fs v ds = 15 v, i d = 15 a 75 s dynamic b input capacitance c iss v ds = 20 v, v gs = 0 v, f = 1 mhz 2400 pf output capacitance c oss 260 reverse transfer capacitance c rss 100 total gate charge q g v ds = 20 v, v gs = 10 v, i d = 20 a 37 56 nc v ds = 20 v, v gs = 4.5 v, i d = 20 a 16 24 gate-source charge q gs 6.5 gate-drain charge q gd 4.5 gate resistance r g f = 1 mhz 2.5 5.5 8.5 : tu r n - o n d e l ay t i m e t d(on) v dd = 20 v, r l = 1 : i d # 20 a, v gen = 4.5 v, r g = 1 : 30 45 ns rise time t r 15 25 turn-off delay time t d(off) 45 70 fall time t f 15 25 tu r n - o n d e l ay t i m e t d(on) v dd = 20 v, r l = 1 : i d # 20 a, v gen = 10 v, r g = 1 : 915 rise time t r 510 turn-off delay time t d(off) 40 60 fall time t f 510 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 40 a pulse diode forward current a i sm 100 body diode voltage v sd i s = 10 a 0.81 1.2 v body diode reverse recovery time t rr i f = 20 a, di/dt = 100 a/s, t j = 25 c 22 35 ns body diode reverse recovery charge q rr 14 25 nc reverse recovery fall time t a 11 ns reverse recovery rise time t b 11
typical characteristics 25 c, unless otherwise noted output characteristics transfer characteristics capacitance 0 20 40 60 8 0 100 0.0 0.5 1.0 1.5 2.0 2.5 v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d v gs =10 v thr u 5 v v gs =3 v v gs =4 v 0.0 0.3 0.6 0.9 1.2 1.5 012345 v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d t c = 25 c t c = 125 c t c = - 55 c 0 8 00 1600 2400 3200 0 5 10 15 20 c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) c oss c rss transfer characteristics on-resistance vs. drain current gate charge 0 20 40 60 8 0 100 012345 v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d t c = 25 c t c = 125 c t c = - 55 c 0.004 0.006 0.00 8 0.010 0.012 0 204060 8 0 100 - on-resistance ( ) r ds(on) i d - drain c u rrent (a) v gs =10 v v gs =4.5 v 0 2 4 6 8 10 010203040 - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs v ds =30 v v ds =10 v i d =20a v ds =20 v SUD50N04-8M8P n-channel 40 v (d-s) mosfet www.freescale.net.cn 3 / 9 document number: 68647 s10-0109-rev. b, 18-jan-10 www.vishay.com 3 vishay siliconix SUD50N04-8M8P typical characteristics 25 c, unless otherwise noted output characteristics transfer characteristics capacitance 0 20 40 60 8 0 100 0.0 0.5 1.0 1.5 2.0 2.5 v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d v gs =10 v thr u 5 v v gs =3 v v gs =4 v 0.0 0.3 0.6 0.9 1.2 1.5 012345 v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d t c = 25 c t c = 125 c t c = - 55 c 0 8 00 1600 2400 3200 0 5 10 15 20 c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) c oss c rss transfer characteristics on-resistance vs. drain current gate charge 0 20 40 60 8 0 100 012345 v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d t c = 25 c t c = 125 c t c = - 55 c 0.004 0.006 0.00 8 0.010 0.012 0 204060 8 0 100 - on-resistance ( ) r ds(on) i d - drain c u rrent (a) v gs =10 v v gs =4.5 v 0 2 4 6 8 10 010203040 - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs v ds =30 v v ds =10 v i d =20a v ds =20 v
typical characteristics 25 c, unless otherwise noted on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage single pulse, junction-to-ambient 0.5 0. 8 1.1 1.4 1.7 2.0 - 50 - 25 0 25 50 75 100 125 150 t j -j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on) i d =20a v gs =10 v v gs =4.5 v 0.005 0.010 0.015 0.020 0.025 0.030 0246 8 10 - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) t j = 25 c t j = 125 c i d =7.2a 0 100 200 300 400 500 0.0001 0.001 0.01 0.1 1 10 time (s) po w er ( w ) t a = 25 c source-drain diode forward voltage threshold voltage safe operating area, junction-to-case 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 v sd -so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s 1 0.01 0.001 0.1 10 100 t j = 25 c t j = 150 c t j = - 55 c - 1.0 - 0.6 - 0.2 0.2 0.6 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v ariance ( v ) v gs(th) t j - temperat u re (c) i d =1ma 0.01 0.1 1 10 100 1000 0.1 1 10 100 - drain c u rrent (a) i d v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified 10 ms, 100 ms, dc 1ms t c = 25 c single p u lse 100 s b v dss limited b yr ds(on) * 10 s SUD50N04-8M8P n-channel 40 v (d-s) mosfet www.freescale.net.cn 4 / 9 www.vishay.com 4 document number: 68647 s10-0109-rev. b, 18-jan-10 vishay siliconix SUD50N04-8M8P typical characteristics 25 c, unless otherwise noted on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage single pulse, junction-to-ambient 0.5 0. 8 1.1 1.4 1.7 2.0 - 50 - 25 0 25 50 75 100 125 150 t j -j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on) i d =20a v gs =10 v v gs =4.5 v 0.005 0.010 0.015 0.020 0.025 0.030 0246 8 10 - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) t j = 25 c t j = 125 c i d =7.2a 0 100 200 300 400 500 0.0001 0.001 0.01 0.1 1 10 time (s) po w er ( w ) t a = 25 c source-drain diode forward voltage threshold voltage safe operating area, junction-to-case 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 v sd -so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s 1 0.01 0.001 0.1 10 100 t j = 25 c t j = 150 c t j = - 55 c - 1.0 - 0.6 - 0.2 0.2 0.6 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v ariance ( v ) v gs(th) t j - temperat u re (c) i d =1ma 0.01 0.1 1 10 100 1000 0.1 1 10 100 - drain c u rrent (a) i d v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified 10 ms, 100 ms, dc 1ms t c = 25 c single p u lse 100 s b v dss limited b yr ds(on) * 10 s
typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating*, junction-to-case 0 15 30 45 60 0 255075100125150 t c - case temperat u re (c) i d - drain c u rrent (a) package limited power derating, junction-to-ambient 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 150 t j -j u nction temperat u re (c) po w er ( w ) power derating, junction-to-case 0 10 20 30 40 50 60 70 0 25 50 75 100 125 150 t j -j u nction temperat u re (c) po w er ( w ) SUD50N04-8M8P n-channel 40 v (d-s) mosfet www.freescale.net.cn 5 / 9 document number: 68647 s10-0109-rev. b, 18-jan-10 www.vishay.com 5 vishay siliconix SUD50N04-8M8P typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating*, junction-to-case 0 15 30 45 60 0 255075100125150 t c - case temperat u re (c) i d - drain c u rrent (a) package limited power derating, junction-to-ambient 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 150 t j -j u nction temperat u re (c) po w er ( w ) power derating, junction-to-case 0 10 20 30 40 50 60 70 0 25 50 75 100 125 150 t j -j u nction temperat u re (c) po w er ( w )
typical characteristics 25 c, unless otherwise noted normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 0.05 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 single p u lse t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja = 8 0c/ w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted d u ty cycle = 0.5 0.02 normalized thermal transient impedance, junction-to-case 10 -3 10 -2 0 1 1 10 -1 10 -4 0.2 0.1 d u ty cycle = 0.5 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 single p u lse 0.02 0.05 SUD50N04-8M8P n-channel 40 v (d-s) mosfet www.freescale.net.cn 6 / 9 www.vishay.com 6 document number: 68647 s10-0109-rev. b, 18-jan-10 vishay siliconix SUD50N04-8M8P typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?68647 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 0.05 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 single p u lse t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja = 8 0c/ w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted d u ty cycle = 0.5 0.02 normalized thermal transient impedance, junction-to-case 10 -3 10 -2 0 1 1 10 -1 10 -4 0.2 0.1 d u ty cycle = 0.5 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 single p u lse 0.02 0.05
to-252aa case outline note ? dimension l3 is for reference only. l2 d l1 l3 b b1 e1 e1 d1 a1 c a2 gage plane height (0.5 mm) e b2 e c1 a l h millimeters inches dim. min. max. min. max. a 2.21 2.38 0.087 0.094 a1 0.89 1.14 0.035 0.045 a2 0.030 0.127 0.001 0.005 b 0.71 0.88 0.028 0.035 b1 0.76 1.14 0.030 0.045 b2 5.23 5.44 0.206 0.214 c 0.46 0.58 0.018 0.023 c1 0.46 0.58 0.018 0.023 d 5.97 6.22 0.235 0.245 d1 4.10 4.45 0.161 0.175 e 6.48 6.73 0.255 0.265 e1 4.49 5.50 0.177 0.217 e 2.28 bsc 0.090 bsc e1 4.57 bsc 0.180 bsc h 9.65 10.41 0.380 0.410 l 1.40 1.78 0.055 0.070 l1 0.64 1.02 0.025 0.040 l2 0.89 1.27 0.035 0.050 l3 1.15 1.52 0.040 0.060 ecn: t11-0110-rev. l, 18-apr-11 dwg: 5347 SUD50N04-8M8P n-channel 40 v (d-s) mosfet www.freescale.net.cn 7 / 9 document number: 71197 www.vishay.com 18-apr-11 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package information vishay siliconix
recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index SUD50N04-8M8P n-channel 40 v (d-s) mosfet www.freescale.net.cn 8 / 9 application note 826 vishay siliconix document number: 72594 www.vishay.com revision: 21-jan-08 3 application note recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index
SUD50N04-8M8P n-channel 40 v (d-s) mosfet www.freescale.net.cn 9 / 9 disclaimer material category policy all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. freestyle intertechnology, inc., its affiliates, agents, and employees, and all persons acting on it s or their behalf (collectively, ?freestyle?), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. freestyle makes no warranty, representation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on freestyle?s knowledge of typical requirements that are often placed on freestyle products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customer?s responsib ility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customer?s technical experts. product specifications do not expand or otherwise modify freestyle?s terms and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, freestyle products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the freestyle product could result in personal injury or death. customers using or selling freestyle products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold freestyle and its distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay freestyle intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the european parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - 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recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.
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